Buried channel vertical double diffusion mos device

Abstract

A buried channel vertical double-diffusion MOS (buried channel VDMOS) device comprising a substrate, a drain region, a gate region, a source region and a channel region. The drain region is located above the substrate and the gate region is above the substrate surface. The source region is located between two neighboring gates in the substrate. The channel region is located above the drain region separated from the gate by a gate-insulating layer. The channel region further includes a main region, a buried channel region, a first region and a second region. The buried channel region is located below the gate-insulating layer. The buried channel region is impurity-doped so that the threshold voltage of the buried channel VDMOS device can be adjusted. The first region is located in the substrate between two neighboring gates, next to the drain region with portion of it extending into the region underneath the gate. The second region is located below the source region and directly under the first region, but the second region does not have direct contact with the source region.