The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 24, 2001
Filed:
Nov. 12, 1997
Bernd Karl-Heinz Appelt, Apalachin, NY (US);
James Russell Bupp, Endwell, NY (US);
Donald Seton Farquhar, Endicott, NY (US);
Ross William Keesler, Endicott, NY (US);
Michael Joseph Klodowski, Endicott, NY (US);
Andrew Michael Seman, Kirkwood, NY (US);
Gary Lee Schild, Endicott, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A printed circuit board comprising a plurality of conductive bumps having substantially coplanar upper surfaces is provided. The circuit board is formed by providing: a substantially planar metallic layer having a first thickness on at least one surface of the dielectric; applying a first photoresist on the metal layer; imaging the first photoresist to define a pattern of conductive bumps; etching the exposed portions of the metal layer to a second thickness to form the conductive bumps; removing the first photoresist; applying a second photoresist to the metal layer; imaging the second photoresist to define a pattern of circuitry; etching the exposed portions of the metal layer to provide the electrical circuitry; and removing the second photoresist. The present invention also provides a method for preparing printed circuit boards wherein two conductive layers that are disposed on opposing sides of a dielectric layer are inter-connected by at least one of the substantially coplanar conductive bumps. The method comprises the additional steps of depositing a second dielectric layer on the substantially coplanar conductive bumps and circuitry; exposing the upper surface of at least one of the conductive bumps; and depositing a second metal layer on the second dielectric layer and the exposed upper surface of the conductive bump. The present invention is also related to a method for preparing a reinforced panel. The method comprises the steps of: applying a metal layer having a first height on at least one surface of a dielectric substrate; applying a first photoresist to the metal layer, imaging the photoresist to provide at least one section of remaining photoresist defining an opening therein and at least one exposed region of the metal layer; etching the exposed region of the metal layer to a second height; and removing the remaining photoresist to provide a multi-layered structure comprising a dielectric layer and a metal layer comprising at least one region having a second height and at least one region having a first height.