The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 2001

Filed:

Apr. 05, 1996
Applicant:
Inventors:

Zheng Xu, Foster City, CA (US);

John Forster, San Francisco, CA (US);

Tse-Yong Yao, Sunnyvale, CA (US);

Jaim Nulman, Palo Alto, CA (US);

Fusen Chen, Cupertino, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C23C 1/434 ;
U.S. Cl.
CPC ...
C23C 1/434 ;
Abstract

An aluminum sputtering process, particularly useful for filling vias and contacts of high aspect ratios formed through a dielectric layer and also usefull for forming interconnects that are highly resistant to electromigration. A liner or barrier layer is first deposited by a high-density plasma (HDP) physical vapor deposition (PVD, also called sputtering) process, such as is done with an inductively coupled plasma. If a contact is connected at its bottom to a silicon element, the first sublayer of the liner layer is a Ti layer, which is silicided to the silicon substrate. The second sublayer comprises TiN, which not only acts as a barrier against the migration of undesirable components into the underlying silicon but also when deposited with an HDP process and biased wafer forms a dense, smooth crystal structure. The third sublayer comprises Ti and preferably is graded from TiN to Ti. Over the liner layer, an aluminum layer is deposited in a standard, non-HDP process. The liner layer allows the hottest part of the aluminum deposition to be performed at a relatively low temperature between 320 and 500° C., preferably between 350 and 420° C., while still filling narrow plug holes, and the TiN does not need to be annealed to form an effective barrier against diffusion into the silicon. A horizontal interconnect formed by the inventive process is resistant to electromigration.


Find Patent Forward Citations

Xu, Zheng. (2001). Filling narrow apertures and forming interconnects with a metal utilizing a crystallographically oriented liner layer (U.S. Patent No. 6217721). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6217721

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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