The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 10, 2001
Filed:
Jun. 26, 2000
Applicant:
Inventors:
Om P. Agrawal, Los Altos, CA (US);
Herman M. Chang, Cupertino, CA (US);
Bradley A. Sharpe-Geisler, San Jose, CA (US);
Giap H. Tran, San Jose, CA (US);
Bai Nguyen, San Jose, CA (US);
Assignee:
Vantis Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ; G06F 7/38 ; H03K 1/7693 ; H03K 1/9177 ;
U.S. Cl.
CPC ...
G06F 1/750 ; G06F 7/38 ; H03K 1/7693 ; H03K 1/9177 ;
Abstract
A field-programmable gate array device (FPGA) having plural rows and columns of logic function units is organized with symmetrical and complementary Variable Grain Architecture (VGA) and Variable Length Interconnect Architecture (VLI). Synthesis mapping exploits the diversified and symmetric resources of the VGA and VLI to efficiently pack function development into logic units of matched granularity and to transfer signals between logic units with interconnect lines of minimal length.