The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2001

Filed:

Jan. 06, 2000
Applicant:
Inventors:

Teruhiko Amano, Hyogo, JP;

Takahiro Tsuruda, Hyogo, JP;

Kazutami Arimoto, Hyogo, JP;

Tetsushi Tanizaki, Hyogo, JP;

Takeshi Fujino, Hyogo, JP;

Mitsuya Kinoshita, Hyogo, JP;

Fukashi Morishita, Hyogo, JP;

Mako Kobayashi, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 8/00 ;
U.S. Cl.
CPC ...
G11C 8/00 ;
Abstract

A master control circuit provides access to a corresponding memory block via four local control circuits. The memory blocks are arranged so as to surround the master control circuit and the local control circuits. The amount of delay of a control signal to each memory block is set substantially equal to suppress skew in the control signal. A DRAM of high speed can be realized.


Find Patent Forward Citations

Amano, Teruhiko. (2001). High speed operable semiconductor memory device with memory blocks arranged about the center (U.S. Patent No. 6215720). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6215720

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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