The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2001

Filed:

Jan. 25, 1999
Applicant:
Inventors:

Masayoshi Saito, Hachiouji, JP;

Yoshitaka Nakamura, Ome, JP;

Hidekazu Goto, Fussa, JP;

Keizo Kawakita, Ome, JP;

Satoru Yamada, Ome, JP;

Toshihiro Sekiguchi, Hidaka, JP;

Isamu Asano, Iruma, JP;

Yoshitaka Tadaki, Hanno, JP;

Takuya Fukuda, Kodaira, JP;

Masayuki Suzuki, Kokubunji, JP;

Tsuyoshi Tamaru, Hachiouji, JP;

Naoki Fukuda, Ome, JP;

Hideo Aoki, Musashimurayama, JP;

Masayoshi Hirasawa, Ome, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/972 ;
U.S. Cl.
CPC ...
H01L 2/972 ;
Abstract

In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta,O,(tantalum oxide) film,the portions of bit lines BL and first-layer interconnect lines,to,of a peripheral circuit which are in contact with at least an underlying silicon oxide film,are formed of a W film, the bit lines BL and the interconnect lines,to,being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines,to,and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.


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