The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 27, 2001
Filed:
Mar. 16, 1999
Xiao-Yu Li, San Jose, CA (US);
Sunil D. Mehta, San Jose, CA (US);
Vantis Corporation, Sunnyvale, CA (US);
Abstract
A non-volatile memory device includes a floating-gate electrode overlying a tunnel oxide layer. A portion of the floating-gate electrode forms the control gate electrode for a sense transistor that is used to determine the presence of charge on the floating-gate electrode. A composite insulation layer overlies the floating-gate electrode. The composite insulation layer includes a dielectric layer, a doped insulating layer overlying the dielectric layer, and a planarization layer overlying the doped insulating layer. The thicknesses of the dielectric layer and the doped insulating layer are precisely determined, such that the doped insulating layer getters mobile ions, such as hydrogen ions, away from the floating-gate electrode, while not capacitively coupling with the floating-gate electrode. In a preferred embodiment of the invention, the dielectric layer has a thickness of about 450 to about 550 Å, and the doped insulating layer has a thickness of about 2900 to about 3100 Å, and the planarization layer has a thickness of about 6000 to 8000 Å.