The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 27, 2001

Filed:

Jan. 13, 2000
Applicant:
Inventors:

Edward K. Yeh, San Jose, CA (US);

Calvin Todd Gabriel, Cupertino, CA (US);

Samit Sengupta, San Jose, CA (US);

Assignee:

VLSI Technology, Inc, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
C09K 1/300 ;
U.S. Cl.
CPC ...
C09K 1/300 ;
Abstract

A method for preparing a semiconductor substrate for subsequent silicide formation. In one embodiment, the present invention subjects the semiconductor substrate to an ashing environment. In the present embodiment, the ashing environment is comprised of H,O vapor, and a gaseous fluorocarbon or a fluorinated hydrocarbon gas. In so doing, contaminants on the semiconductor substrate are removed. Next, the present invention subjects a mask covering a polysilicon stack to a mask-removal ashing environment. In the present embodiment, the mask-removal ashing environment is comprised of an O,plasma. In so doing, the mask covering the polysilicon stack is removed. As a result, the semiconductor substrate and the top surface of the polysilicon stack are prepared for subsequent silicide formation thereon.


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