The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 20, 2001

Filed:

Dec. 16, 1998
Applicant:
Inventors:

Om P. Agrawal, Los Altos, CA (US);

Bradley A. Sharpe-Geisler, San Jose, CA (US);

Herman M. Chang, Cupertino, CA (US);

Bai Nguyen, San Jose, CA (US);

Giap H. Tran, San Jose, CA (US);

Assignee:

Vantis Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 7/38 ;
U.S. Cl.
CPC ...
G06F 7/38 ;
Abstract

A Variable Grain Architecture (VGA) device includes a shared output component (SOC) that may be used for programmably-routing process result signals onto either or plural ones of differently directed longlines within an FPGA. Plural VGB's make shared use of each SOC to output respective function signals to the longlines. The SOC may be also used for programmably-routing signals (e.g., feedthrough signals) that are selectively acquired from either one of equivalent but differently positioned interconnect channels. Such freedom in routing VGB result signals or feedthrough signals can allow FPGA configuring software to explore a wider range of partitioning, placement and/or routing options for finding optimized implementations in the VGA FPGA device of various, supplied design specifications.


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