Method of making an igfet with elevated source/drain regions in close proximity to gate with sloped sidewalls

Abstract

An IGFET with elevated source and drain regions in close proximity to a gate with sloped sidewalls is disclosed. A method of making the IGFET includes forming a lower gate level over a semiconductor substrate, wherein the lower gate level includes a top surface, a bottom surface and sloped opposing sidewalls, and the top surface has a substantially greater length than the bottom surface, and depositing a semiconducting layer on the lower gate level and on underlying source and drain regions of the semiconductor substrate to form an upper gate level on the lower gate level, an elevated source region on the underlying source region, and an elevated drain region on the underlying drain region. The elevated source and drain regions are separated from the lower gate level due to a retrograde slope of the sidewalls of the lower gate level, and the elevated source and drain regions are separated from the upper gate level due to a lack of step coverage in the semiconducting layer. The method also includes implanting a dopant into the elevated source and drain regions, and diffusing the dopant from the elevated source and drain regions into the underlying source and drain regions. Preferably, the semiconducting layer is deposited by epitaxial deposition, the lower gate level is substantially thicker than the semiconducting layer, the elevated source and drain regions include sidewalls beneath and substantially aligned with sidewalls of the upper gate level, and all source/drain doping in the underlying source and drain regions is diffused from the elevated source and drain regions. In this manner, a highly miniaturized IGFET can be provided with shallow channel junctions without the need for sidewall spacers adjacent to the gate.