Method of forming a node contact of a dram's memory cell

Abstract

This invention provides a method of forming a node contact with self-alignment on a semiconductor wafer. The wafer comprises a substrate, a dielectric layer, and a first and a second bit lines. A first side wall of the first bit line is adjacent to a second side wall of the second bit line and comprises a first region and two second regions adjacent to the first region. The distance between the first region and the second side wall is greater than a predetermined value and the distance between the two second regions and the second side wall is less than the predetermined value. A second insulating layer is formed on the dielectric layer and two bit lines to form a groove over the gap between the first region and the second side wall. A first anisotropic etching is performed to extend the bottom of the groove down to the dielectric layer. The remaining second insulating layer around the groove forms a spacer, and the remaining second insulating layer in the gaps between the two second regions and the second side wall still completely covers the surface of the two gaps. A second anisotropic etching process is performed to remove the dielectric layer at the bottom of the groove in a vertical direction down to the substrate so as to form the node contact.