The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 06, 2001
Filed:
Oct. 13, 1999
Gerald R. Dietze, Portland, OR (US);
Oleg V. Kononchuk, Brush Prairie, WA (US);
SEH America, Inc., Vancouver, WA (US);
Abstract
An improved method is provided for processing the backside of a wafer within an epitaxial reactor chamber, such as by etching the backside of the wafer or applying a back seal to the backside of the wafer. The backside of the wafer can therefore be processed within the reactor chamber and an epitaxial layer can then be deposited on the front side of the wafer without ever removing the wafer from the epitaxial reactor chamber. In one embodiment, the backside of the wafer is processed by applying a back seal layer to the backside of the wafer. The back seal layer can be applied by either passing a gas over the backside of the wafer or by setting the wafer upon a sacrificial wafer. In either instance, the gas or the sacrificial wafer reacts with the wafer to grow the back seal layer on the backside of the wafer. In another embodiment, the backside of the wafer is processed by etching the backside of the wafer, such as by passing a reactive gas over the backside of the wafer. Once the backside of the wafer has been processed, such as by applying a back seal layer or by etching the backside of the wafer, an epitaxial layer is deposited on the front side of the wafer without ever removing the wafer from the epitaxial reactor chamber, thereby reducing the cost and fabrication time of the resulting wafers.