Method to fabricate the mos gate

Abstract

A new method for forming a feature, such as a gate electrode, having a feature size, or a line width, controlled by spacer width and not limited by photolithographic resolution is described. A dielectric stack is provided on the surface of a semiconductor substrate. The dielectric stack is etched away where it is not covered by a mask wherein the remaining dielectric stack has a width equal to the spacing between two of gate electrodes to be formed. A gate oxide layer is grown on the surface of the semiconductor substrate not covered by the dielectric stack. A polysilicon layer is deposited overlying the gate oxide layer and the dielectric stack. The polysilicon layer is etched back to leave spacers on the sidewalls of the dielectric stack. A dielectric layer is deposited overlying the substrate and polished back whereby an upper portion of the dielectric stack and the spacers are polished away. The remaining dielectric layer and the dielectric stack ar removed whereby the spacers remain forming narrow gate electrodes having the gate oxide layer thereunder to complete fabrication of gate electrodes in the manufacture of an integrated circuit device. This process can be integrated with a conventional lithographic process for forming wide gate electrodes as well.