The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 06, 2001
Filed:
Dec. 23, 1997
Craig S. Lage, Austin, TX (US);
Mousumi Bhat, Austin, TX (US);
Yeong-Jyh Tom Lii, Austin, TX (US);
Andrew G. Nagy, Austin, TX (US);
Larry E. Frisa, Radebeul bei Dresden, DE;
Stanley M. Filipiak, Pflugerville, TX (US);
David L. O'Meara, Austin, TX (US);
T. P. Ong, Austin, TX (US);
Michael P. Woo, Austin, TX (US);
Terry G. Sparks, Austin, TX (US);
Carol M. Gelatos, Redwood City, CA (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (,and,), wherein each local interconnect (,) cross couples the inverters of the SRAM and is formed within a single opening (,). Also, interconnect portions (,) of word lines are laterally offset from silicon portions (,) of the same word line, so that the interconnect portions do not interfere with bit line connections.