The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 23, 2001
Filed:
Dec. 23, 1999
Kuen-Yow Lin, Chia-I, TW;
Horng-Nan Chern, Chia-Li Chen, TW;
United Microelectronics Corp., Hsin-Chu, TW;
Abstract
A method for forming a capacitor of memory cell is disclosed. The method includes, firstly, there is a semiconductor substrate that owns a first dielectric layer formed thereon. The first dielectric layer has a contact opening filled with doped polysilicon to form a stud. Then, a second dielectric layer is formed on the first dielectric layer and the surface of the stud. A silicon oxynitride (SiON) layer can be formed on the second dielectric layer. A photoresist layer is formed on the silicon oxynitride layer. Portions of the silicon oxynitride layer and the second dielectric layer are etched. Blanket and conformably forming an amorphous silicon layer is carried out. A third dielectric layer is formed on the amorphous silicon layer. The third dielectric layer and a portion of the amorphous silicon layer atop of the silicon oxynitride layer are all etched back. The silicon oxynitride layer is used as an anti-etching layer. The amorphous silicon layer will be treated to form a hemispherical-grained (HSG) layer on the surface of the amorphous silicon layer. The silicon oxynitride layer is removed. Dipping the surface of the second dielectric layer is achieved to comprehensively clean the surface thereof, thereby preventing unwanted connection of the hemispherical-grained layer on the capacitor with the hemispherical-grained layer out of the capacitor.