Method of fabricating self-aligned split gate flash memory cell

Abstract

A technique for forming an integrated circuit device having a self-aligned gate layer. The method includes a variety of steps such as providing a substrate (,), which is commonly a silicon wafer. Field isolation regions (,) including a first isolation region and a second isolation region are defined in the semiconductor substrate. A recessed region is defined between the first and second isolation regions. The isolation regions (,) are made using a local oxidation of silicon process, which is commonly called LOCOS, but can be others. A thickness of material (,) such as polysilicon is deposited overlying or on the first isolation region, the second isolation region, and the active region. A step of selectively removing portions of the thickness of material overlying portions of the first isolation region and the second isolation region is performed, where the removing step forms a substantially planar material region in the recessed region. The substantially planar material region is self-aligned into the recessed region using the removing step.