Integrated circuit memory with a bus transceiver

Abstract

A two port high speed integrated circuit memory device that includes a bus transceiver, a memory array and a decoder. The present invention provides a processor high speed access to the internal memory array via very low capacitive load address and data buses. The present invention also buffers a secondary bus to provide access to slower-speed local devices. The bus transceiver transfers address, data and control signals between the primary and secondary port and also couples signals to the internal memory array. The bus transceiver includes an input data bus, an output data bus, and an address and control bus. Each of these separate buses include a buffer at the primary and secondary port to minimize capacitive loading. The decoder in the two port memory device decodes memory chip select signals and control signals that define the operational mode of the device. To save power the present invention provides an operational mode in which primary bus signals are not reflected to the secondary bus unless the internal memory array is not selected by the chip selects. In an enhanced mode the two port memory device includes a ready signal generator feature, and chip select lines are converted into additional address input lines.