The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2000

Filed:

Mar. 20, 1998
Applicant:
Inventors:

Tsung-Ju Yang, Chutung Hsinchu, TW;

Chien-Mei Wang, Taipei, TW;

Tsung-Kuei Kang, Hsin-chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G03F / ;
U.S. Cl.
CPC ...
430313 ; 430317 ; 438622 ;
Abstract

The present invention is a method for making intermetal dielectrics (IMD) on integrated circuits using a low dielectric constant (low k) spin-on polymers without via hole poisoning. A patterned conductive layer is used to form metal interconnection for the integrated circuits. A IMD layer is then formed by depositing sequentially three IMD layers, IMD1, IMD2 and IMD3 respectively. The IMD1 is deposited first and is a low k polymer. IMD2 composed of silicon nitride (Si.sub.3 N.sub.4) and a thick IMD3 composed of silicon oxide (SiO.sub.2) is deposited next. The IMD3 is planarized, and a photoresist mask is used to pattern openings in IMD3 to form a hard mask for etching the remaining via holes in IMD2 and IMD3. The IMD2 layer protects the low k polymer (IMD1) from damage while plasma ashing in oxygen is used to removal the photoresist mask. This method circumvents the problems with more conventional processing in which the low k polymer exposed in the via hole during oxygen plasma removal of the photoresist results in a porous and highly hygroscopic polymer leading to via hole poisoning. In a second approach a thick low k polymer layer (IMD1) is planarized and the PECVD silicon oxide (IMD2) a nd a PECVD silicon nitride (IMD3) is deposited and then the via holes are etched as in the first approach using IMD3 as a hard mask.


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