The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2000

Filed:

Sep. 08, 1998
Applicant:
Inventors:

Yinon Degani, Highland Park, NJ (US);

Thomas Dixon Dudderar, Chatham, NJ (US);

Robert Charles Frye, Piscataway, NJ (US);

King Lien Tai, Berkely Heights, NJ (US);

Assignee:

Lucent Technologies Inc., Murray Hill, NJ (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K / ;
U.S. Cl.
CPC ...
361767 ; 361772 ; 361774 ; 257723 ; 257776 ; 257777 ; 257778 ; 438108 ;
Abstract

The specification describes a recessed chip IC package in which the IC chip is bonded to a translator, and power and ground planes for IC power and ground interconnections are formed on separate interconnect levels of the translator. The multilevel interconnection capability of the translator allows crossovers, and allows power and ground pins from the IC chip to be both isolated from signal I/Os, and consolidated into fewer interconnections going to the next board level. The translator also has a large area outboard of the IC chip area to allow fan out from high pin count chips to large pitch interconnection sites for interconnection to the next board level.


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