The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 28, 2000
Filed:
Sep. 05, 1997
Darin A Chan, Campbell, CA (US);
Steven C Avanzino, Cupertino, CA (US);
Subramanian Venkatkrishnan, Sunnyvale, CA (US);
Minh Van Ngo, Union City, CA (US);
Christy Mei-Chu Woo de la Girond'arc, Cupertino, CA (US);
Diana M Schonauer, San Jose, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A multiple-layer interconnect structure in an integrated circuit, is formed using damascene techniques. A first layer interconnect has a first dielectric layer through which at least one first layer conductor extends. A second layer interconnect is then formed on the first layer interconnect. The second layer interconnect also includes a second layer dielectric through which at least one second layer conductor extends. However, the second layer interconnect is created by first forming a thick second later dielectric layer and then reducing the thickness of the second layer dielectric prior to a patterning step. As a result topographical irregularities that may have carried over to the second layer interconnect from the first layer interconnect are removed by providing a substantially planar surface on the second layer dielectric.