The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 24, 2000
Filed:
Aug. 04, 1999
Taiwan Semiconductor Manufacturing Company, Hsin-Chu, TW;
Abstract
A method for forming a self aligned contact wherein a dielectric layer is formed directly on a conductive structure according the present invention. A semiconductor structure having a polysilicon conductive structure (such as a bit line) thereon is provided. A contact area is located on the semiconductor structure adjacent to the conductive structure. A dielectric layer, preferably composed of silicon oxide is formed over the conductive structure and the semiconductor structure. A top hard mask layer is formed over the dielectric layer. A contact opening is formed in the top hard mask layer and the dielectric layer using an etch selective to oxide over polysilicon, thereby exposing the contact region of the semiconductor structure adjacent to the conductive structure without etching through the conductive structure. A first lining dielectric layer, a second lining dielectric layer, and a third lining dielectric layer are sequentially deposited on the sidewalls of the contact opening and on the contact area of the semiconductor structure. The first and third lining dielectric layers are preferably composed of silicon dioxide and the third lining dielectric layer is preferably composed of silicon nitride. The third lining dielectric layer is anisotropically etched forming a second contact opening in the second lining dielectric layer over the contact area while leaving a spacer on the sidewall of the contact opening. The second lining dielectric layer and the first lining dielectric layer are anisotropically etched to expose the contact area of the semiconductor structure, while the spacer prevents erosion of the second lining dielectric layer and the first lining dielectric layer on the sidewall of the contact opening. The remaining spacer is removed, preferably using a buffered HF dip. A polysilicon contact layer is formed on the second lining dielectric layer and on the contact area of the semiconductor structure.