Gate micro-patterning process

Abstract

A new method of forming sub-micron features, such as a gate feature in particular, of less than 0.25 micrometers (.mu.m) to 0.18 .mu.m employing a micro-patterning process is disclosed. It is shown that the critical dimension width of a polysilicon gate can be controlled precisely by using very thin lithographic layers in a micro-patterning process. This is accomplished by forming a conductive layer over a gate oxide layer, followed by forming a planarization layer, an anti-reflective coating (ARC), and then, as a key feature, a very thin photoresist layer. A high resolution photoresist mask is next formed without the presence of any reflections in the photoresist layer due to the high optical absorptivity of the ARC, or BARC, at the bottom of the photoresist layer. Then, the precisely formed pattern is successively transferred, by etching, to BARC and to planarization layers which in turn form as second and first hard masks, respectively. In a first embodiment, the thin photoresist layer along with the BARC layer are removed simultaneously with the forming of the gate electrode in the conductive layer. In the second embodiment, the photoresist mask as well as the second hard mask are removed simultaneously with the forming of the gate electrode in the conductive layer.