Method of making self-aligned flash memory cell to prevent source line

Abstract

A process for making stacked gate memory cells which does not require the extra thermal cycle as in the conventional SAMOS process. It includes the steps of: (a) forming a silicon nitride layer on a wafer surface; (b) forming a diffusion pattern mask on the silicon nitride layer which includes a source line diffusion mask; (c) removing portions of the silicon nitride layer not covered by the diffusion pattern mask to expose a portion of the silicon substrate; (d) removing the diffusion pattern mask; (e) using the remaining portion of the silicon nitride as a mask to grow a field oxide layer in the silicon substrate; (f) forming a poly-1 layer, an interpoly dielectric layer, and a poly-2 layer on the wafer surface; (f) forming a SAMOS (self-aligned MOS) mask which contains a plurality of SAMOS strips perpendicular to the poly-1 strips, followed by SAMOS etching to form a plurality of stacked gates. The source diffusion mask is formed to have such a predetermined width that the field oxide layer is formed to contain bird beaks which merge with each other to form an interconnected field oxide bird's beak. Further, the interconnected field oxide bird's beak is formed to be thicker than the thickness of the interpoly dielectric layer so as to protect the portion of the silicon substrate not covered by the poly-1 strips from being trenched during the SAMOS etching process.