The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 10, 2000
Filed:
Jul. 23, 1997
Shumpei Kawasaki, Tokyo, JP;
Eiji Sakakibara, Kodaira, JP;
Kaoru Fukada, Koganei, JP;
Takanaga Yamazaki, Kodaira, JP;
Yasushi Akao, Kokubunji, JP;
Shiro Baba, Kokubunji, JP;
Toshimasa Kihara, Tachikawa, JP;
Keiichi Kurakazu, Tokorozawa, JP;
Takashi Tsukamoto, Kodaira, JP;
Shigeki Masumura, Kodaira, JP;
Yasuhiro Tawara, Kodaira, JP;
Yugo Kashiwagi, Koganei, JP;
Shuya Fujita, Kodaira, JP;
Katsuhiko Ishida, Koganei, JP;
Noriko Sawa, Tama, JP;
Yoichi Asano, Tokyo, JP;
Hideaki Chaki, Tokorozawa, JP;
Tadahiko Sugawara, Kodaira, JP;
Masahiro Kainaga, Yokohama, JP;
Kouki Noguchi, Kokubunji, JP;
Mitsuru Watabe, Ibaragi, JP;
Hitachi, Ltd., Tokyo, JP;
Hitachi VLSI Engineering Corp., Tokyo, JP;
Hitachi Microcomputer System, Ltd., Tokyo, JP;
Abstract
Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.