Method for making deep sub-micron mosfet structures having improved

Abstract

A method for making improved MOSFET structures is achieved. A Si.sub.3 N.sub.4 and a SiO.sub.2 layer are deposited and patterned to have openings for gate electrodes over device areas on a substrate. A second Si.sub.3 N.sub.4 layer is deposited and etched back to form arc-shaped sidewall spacers in the openings. An anti-punchthrough implant and a gate oxide are formed in the openings between the Si.sub.3 N.sub.4 sidewall spacers. A polysilicon layer is deposited and polished back to form gate electrodes. The SiO.sub.2 and the Si.sub.3 N.sub.4 layers, including the sidewall spacers, are removed to form free-standing gate electrodes that increase in width with height, and having arc-shaped sidewalls. An implant through the edges of the arc-shaped gate electrodes results in lightly doped source/drains that are graded both in junction depth and dopant concentration to reduce hot electron effects. A second SiO.sub.2 layer is deposited and etched back to form insulating sidewall spacers that include air spacers to reduce the gate-to-drain capacitance. Another implant is used to form source/drain contact areas. A salicide process is used which forms a silicide on the polysilicon gate electrodes and on the source/drain contact areas. The arc-shaped structure allows MOSFETs to be formed with reduced channel lengths while maintaining a wider silicide area on the gate electrodes for reduced resistance.