Reduction of a hot carrier effect by an additional furnace anneal

Abstract

A process for fabricating an I/O device, comprised with an LDD source/drain region, featuring a graded dopant profile, and simultaneously fabricating a core device, comprised with an LDD source/drain region, featuring a sharp dopant profile, has been developed. The process features the initial creation of the I/O device, LDD source/drain region, via an ion implantation procedure, followed by a furnace anneal procedure, to initiate transient enhanced diffusion, resulting in a graded dopant profile, for the I/O device, LDD source/drain region. The graded dopant profile, affords reduced risk of hot carrier effects, prevalent with the higher voltage, I/O devices. The creation of the core device, LDD source/drain region, is next addressed via another ion implantation, followed by a RTA procedure, used to activate the implanted species, and to create an LDD source/drain region, for the core device, featuring a sharp dopant profile, needed for performance objectives. The creation of insulator spacers, on the sides of the gate structures, is followed by the formation of heavily doped source/drain regions, for both I/O, and core devices.