Etch back method for smoothing microbubble-generated defects in

Abstract

The present invention relates to the fabrication of semiconductor devices and more particularly to a new method for avoiding abnormal via holes when Spin On Glass, SOG, is used as a means of planarizing an interlevel metal interconnect structure. The invention addresses the problem of locations of micro bubbles in a SOG layer that can lead to seams, voids and a ragged surface topology which, in turn, can make it very difficult to eventually etch well formed via holes at such locations. The invention details a new etch back method that solves the above problem by properly smoothing the micro bubble locations. This new method includes a sequence of anisotropic and isotropic etching steps that are used to partially etch back the cured SOG layer in order to achieve a planarized surface while also smoothing the micro bubble locations in the cured SOG layer. By having first smoothed out the micro bubble locations, it is then possible to deposit an overlying conventional CVD oxide layer without creating highly detrimental seams and voids above the original micro bubble locations. By greatly minimizing such seams and voids, and their associated tendency for uncontrollable etching behavior, proper etching of via holes is now achievable above the original micro bubble locations and the above problem of abnormal via holes is solved.