The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 29, 2000
Filed:
Sep. 08, 1997
Prabhakar P Tripathi, Santa Clara, CA (US);
Keith Chao, San Jose, CA (US);
Ratan K Choudhury, Milpitas, CA (US);
Gauri C Das, San Jose, CA (US);
Nicholas K Eib, San Jose, CA (US);
Ashok K Kapoor, Palo Alto, CA (US);
Thomas G Mallon, Santa Clara, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
Disclosed is the formation of additional lines, either dummy lines or active lines, in an electrically conductive pattern of lines to provide more uniform loading for either etching or chemical/mechanical polishing of a layer of electrically conductive material from which the pattern of lines is formed. Also disclosed is the use of additional or dummy vias to balance the loading during etching of the vias, as well as to provide stress relief for underlying metal in regions or areas having a low density of vias. Further disclosed is the use of a working grid on the integrated circuit structure to analyze the spacing of lines or vias for the above effects.