Method for forming a trench isolation structure in an integrated circuit

Abstract

A method is provided for forming a trench isolation structure in an integrated circuit that has a better reliability and an acceptable time-dependent dielectric breakdown over a greater range of production. The manufacturing method involves etching a trench in a semiconductor substrate, forming a sidewall-insulating layer along the sidewall and bottom of the trench, and depositing a trench-insulating layer in the trench and over the semiconductor substrate. The sidewall-insulating layer is formed to have a lower etch rate than the trench-insulating layer. As a result of this difference in etch rates, the sidewall-insulating layer is not damaged too much during wet etching processes that take place during the later part of manufacture. This makes the interface between the substrate, sidewall-insulating layer, and gate oxide more reliable. The difference in etching rate can be obtained by keeping an annealing process used in later processing below a threshold temperature so that the etch rate of the trench-isolating layer does fall too low. The difference in etching rate can also be obtained by using different materials for the sidewall-isolating layer and the trench-isolating layer, or by using multiple annealing processes.