The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2000

Filed:

Dec. 17, 1998
Applicant:
Inventor:

Weiching Horng, Tai-Chung, TW;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438262 ; 438296 ; 438529 ;
Abstract

A flash memory structure is formed by a method comprising the steps of providing a semiconductor substrate, and then forming a shallow first trench within the substrate. Thereafter, a buried doped region is formed underneath the first trench so that the buried doped region is at a distance from the substrate surface. The buried doped region is one major aspect in this invention that can be applied to the processing of shallow trench isolation and is capable of reducing device area. Next, a deeper second trench is etched in the substrate. The second trench has a greater depth than the depth of the first trench. Subsequently, insulating material is deposited into the first and the second trench, and then a stacked gate structure is formed above the substrate. Later, the surface source region and drain region are formed on two sides of the stacked gate structure. Through thermal operation, the surface source region alternately connects with the buried doped region to form a buried common source region.


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