The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 08, 2000
Filed:
Aug. 22, 1997
Alfons Vindasius, Saratoga, CA (US);
Marc E Robinson, San Jose, CA (US);
William R Scharrenberg, Los Altos Hills, CA (US);
Cubic Memory, Inc., Scotts Valley, CA (US);
Abstract
A flip chip on chip method for forming a flip chip assembly including a first flip chip; a second flip chip directly connected to the top of the first flip chip; and electrically conductive epoxy means disposed between the second flip chip and the top of the first flip chip to form an electrical connection between the first flip chip and the second flip chip. In another preferred embodiment, a method for forming a flip chip assembly including a plurality of semiconductor chips where the plurality of chips are vertically interconnected on top of one another to form an electrically interconnected stack of chips; a flip chip directly connected to the top chip of the stack of chips; and electrically conductive epoxy means disposed between said flip chip and said top chip to form an electrical connection between the flip chip and the top chip. In still another preferred embodiment, a method of forming a flip chip assembly including a semiconductor wafer having a plurality of first flip-chips formed thereon; a plurality of second flip chips, each one of the second flip chips directly connected to a respective one of the plurality of first flip-chips; and electrically conductive epoxy means disposed between the respective first flip-chip and second flip-chip connections to form an electrical connection between the respective first flip-chip and second flip chip connections.