The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2000

Filed:

Jun. 30, 1999
Applicant:
Inventors:

Andrew K Chan, Palo Alto, CA (US);

James M Apland, Gilroy, CA (US);

Ket-Chong Yap, Fremont, CA (US);

Assignee:

QuickLogic Corporation, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365203 ; 365154 ;
Abstract

A random access memory (RAM) device includes a buffer in the memory cell to isolate the latching circuit from the read bit line. Consequently, read disturb errors caused by capacitive loading on the read bit line are avoided. Further, the precharge requirements on the write bit line are simplified because the buffer permits optimization of the latching circuit in the memory cell. The RAM device includes a precharge circuit that precharges the write bit line to a ground reference voltage prior to performing write operations. By precharging the write bit line to ground reference voltage, write disturb problems caused by capacitive loading on the write bit line are avoided. Further, by coupling the write bit line to ground reference voltage, little or no power is consumed by precharging the write bit line.


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