Algorithmic pattern generator for integrated circuit tester

Abstract

An integrated circuit (IC) tester organizes an IC test into a succession of test cycles, each test cycle being subdivided into four segments. The tester includes a separate tester channel for carrying out a test activity at each IC pin during each segment of the test cycle. The tester also includes a separate pattern generator for each channel. Each pattern generator concurrently generates four vectors at the start of each test cycle. Each vector tells the channel what activity it is to carry out during a separate segment of the test cycle. Each pattern generator includes a low-speed vector memory storing large blocks of vectors at each address and a cache memory system for caching blocks of vectors read out of the vector memory at a low frequency and then reading vectors out in sets of 16 at the higher test cycle frequency. A vector alignment circuit selects from among the cache memory output vectors to provide the four vectors to the channel for the test cycle. Thus the frequency of test activities carried out by the tester is four times greater than the cache memory read access frequency and many times the vector memory read access frequency. To conserve vector memory space when repetitive vector sequences are to be generated, the cache memory system repeatedly read accesses various vector sequences both in the vector memory and in the cache memory.