The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 04, 2000
Filed:
Jul. 13, 1998
Taiwan Semiconductor Manufacturing Company, Hsin-Chu, TW;
Abstract
A method of forming borderless contacts and vias is disclosed. Borders which are conventionally provided in aligning contacts and vias to device and/or metal regions in a semiconductor device take up too much valuable real estate on semiconductor substrates, and hence reduce productivity of the products. By employing a hard-mask of this invention, and a specific sequence of process steps, alignment can be achieved without the need for borders. First, a thin nitride layer is deposited on an insulating layer formed over a substructure of a substrate having device and/or metal regions. The hard-mask is patterned with metal line openings, and a photoresist layer is formed with contact or via pattern over the already patterned hard-mask. The contact/via openings are etched into the dielectric layer until the substructure is reached. The hole openings are filled plug metal and then partially etched back, leaving a plug in the hole opening. The line trench is etched further into the dielectric layer until metal plug is reached. The trench is then filled with metal, such as aluminum-copper or copper and the excess is removed by chemical-mechanical polishing. Thus, a borderless and self-aligned interconnect comprising plug and metal line is formed.