The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2000

Filed:

May. 07, 1998
Applicant:
Inventors:

Hao-Chieh Liu, Taipei, TW;

Erik S Jeng, Hsinchu, TW;

Bi-Ling Chen, Taipei, TW;

Wan-Yih Lien, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438706 ; 438723 ; 438724 ; 438737 ; 438743 ; 438744 ;
Abstract

A method of forming a plurality of contact holes 70 in a semiconductor wafer uses a single step. The semiconductor wafer includes a dielectric layer 69 overlying a silicon substrate 51, a silicon nitride layer 67a, and a silicon oxynitride layer 63c. First, a photoresist 68 layer is developed on the dielectric layer. Prior to forming the dielectric layer, the silicon oxynitride layer is formed overlying a first conductive layer, and the silicon nitride layer is formed overlying a second conductive layer. Second, an etching step is performed to etch through the silicon oxynitride layer, the silicon nitride layer, a portion of the dielectric layer above the silicon oxynitride layer, and the silicon nitride layer to expose the silicon substrate 51, the first conductive layer 63a, and the second conductive layer 67c. The etching recipe includes a first chemistry and a second chemistry. The first chemistry includes C.sub.2 F.sub.6, C.sub.4 F.sub.8, CH.sub.3 F, and Ar. The second chemistry is chosen from a group including O.sub.2, CO.sub.2, CO and any combination thereof. Thus, a plurality of contact holes is formed above the silicon substrate, the first conductive layer and the second conductive layer.


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