Method of fabricating embedded gate electrodes

Abstract

A method of fabricating an embedded gate electrode is disclosed. The method includes the steps of: Providing a semiconductor substrate; forming a patterned etch resistant mask layer over the semiconductor substrate, wherein the patterned etch resistant mask layer has a first opening for a desired location of a trench; anisotropically etching through the patterned etch resistant mask layer and into the semiconductor substrate, hence forming the trench at the desired location; removing the patterned etch resistant mask layer; depositing a first insulating layer over the semiconductor substrate and filling up the trench; patterning a planarized first insulating layer to define a second opening for the embedded gate electrode; forming a second insulating layer at the bottom of the second opening; depositing a conductive layer over the second insulating layer and filling up the second opening, hence forming the embedded gate electrode; ion implanting the semiconductor substrate to form source/drain regions; forming a spacer on the sidewall of the embedded gate electrode; depositing a refractory metal layer over the entire exposing surface of a resulting structure; and annealing the refractory metal layer to form a silicide layer on the embedded gate electrode and elsewhere on the source/drain regions.