The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 09, 2000
Filed:
Dec. 31, 1997
Applicant:
Inventors:
Jeffrey Lee Miller, Vancouver, WA (US);
James Conary, Aloha, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ; G11C / ;
U.S. Cl.
CPC ...
36523008 ; 711-3 ;
Abstract
A synchronous interface to a self-timed memory array includes one or more address bus inputs and a first latch stage that includes one or more latches. Each of the latches of the first latch stage includes an input coupled to one of the address bus inputs and a first output. The synchronous interface further includes a second latch stage that includes a plurality of latches. Each of the latches of the second latch stage includes an input coupled to one of the first outputs of the first latch stage and a second output coupled to the memory array.