The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 02, 2000
Filed:
Sep. 23, 1997
Atul C Ajmera, Wappingers Falls, NY (US);
Christine Dehm, Wappingers Falls, NY (US);
Anthony G Domenicucci, New Paltz, NY (US);
George G Gifford, Poughkeepsie, NY (US);
Stephen K Loh, Fishkill, NY (US);
Christopher Parks, Beacon, NY (US);
Viraj Y Sardesai, Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Infineon Technologies North America Corporation, San Jose, CA (US);
Abstract
A 'porous barrier' is formed without formation of a discrete barrier layer by enriching grain boundaries of a body of polysilicon with nitrogen to inhibit thermal mobility of silicon species therealong. In a polycide gate/interconnect structure, the reduced mobility of silicon suppresses agglomeration of silicon in a metal silicide layer formed thereon. Since silicon agglomeration is a precursor of a polycide inversion phenomenon, polycide inversion which can pierce an underlying oxide and cause device failure is effectively avoided. The increased thermal stability of polycide structures and other structures including a body of polysilicon thus increases the heat budget that can be withstood by the structure and increases the manufacturing process window imposed by the presence of polysilicon which can be exploited in other processes such as annealing to develop a low resistance phase of refractory metal silicide included in the polycide structure, drive-in annealing for formation of source/drain regions of field effect transistors and the like.