The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 2000

Filed:

Apr. 10, 1997
Applicant:
Inventors:

Toshimitsu Konuma, Kanagawa, JP;

Akira Sugawara, Kanagawa, JP;

Yukiko Uehara, Kanagawa, JP;

Hongyong Zhang, Kanagawa, JP;

Atsunori Suzuki, Kanagawa, JP;

Hideto Ohnuma, Kanagawa, JP;

Naoaki Yamaguchi, Kanagawa, JP;

Hideomi Suzawa, Kanagawa, JP;

Hideki Uochi, Kanagawa, JP;

Yasuhiko Takemura, Kanagawa, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257 66 ; 257383 ; 257384 ; 257324 ; 257408 ; 257410 ; 257412 ; 257401 ; 257 57 ; 257 66 ;
Abstract

A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an loff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.


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