The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 11, 2000
Filed:
Nov. 20, 1998
Makoto Iida, Gunma-ken, JP;
Satoshi Suzuki, Gunma-ken, JP;
Eiichi Iino, Gunma-ken, JP;
Masanori Kimura, Gunma-ken, JP;
Shozo Muraoka, Gunma-ken, JP;
Shin-Etsu Handotai Co., Ltd., Tokyo, JP;
Abstract
A method for producing a silicon single crystal in accordance with the Czochralski method. The single crystal is grown in an N.sub.2 (V) region where a large amount of precipitated oxygen and which is located within an N region located outside an OSF ring region, or is grown in a region including the OSF ring region, N.sub.1 (V) and N.sub.2 (V) regions located inside and outside the OSF ring region, in a defect distribution chart which shows a defect distribution in which the horizontal axis represents a radial distance D (mm) from the center of the crystal and the vertical axis represents a value of F/G (mm.sup.2 /.degree.C..multidot.min), where F is a pulling rate (mm/min) of the single crystal, and G is an average intra-crystal temperature gradient (.degree.C./mm) along the pulling direction within a temperature range of the melting point of silicon to 1400.degree. C. The method allows production of silicon single crystal wafers in which neither FPDs nor L/D defects exist on the wafer surface, and gettering capability stemming from oxygen precipitation is provided over the entire wafer surface, and silicon single crystal wafers wherein OSF nuclei exit but no OSF ring appears when the wafer is subjected to thermal oxidation treatment, neither FPDs nor L/D defects exist on the wafer surface, and gettering capability is provided over the entire wafer surface.