The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2000

Filed:

Jun. 12, 1998
Applicant:
Inventor:

Masuhiro Yamada, Ashikaga, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
714718 ; 714738 ;
Abstract

There is provided a memory testing apparatus which can complete a DC test FOR a memory in a short time period. A pattern generator 2 comprises a hold time setting device 2A for setting a hold time during which a test signal of a predetermined pattern is kept being applied to a memory under test 4, a hold mode control device 2B, activated upon setting of a hold time, for controlling the pattern generator 2 in a hold mode, a DC test start command generating device 2C for generating a DC test start command DCS for starting a DC test of the memory, a pattern end detecting device 2D for detecting when the DC test for the memory is completed, and an end signal generating device 2E for generating a pattern end signal PGEND indicating the completion of the DC test, and there is provided a signal line 5 for transmitting the DC test start command DCS to a DC test unit 3, and further, the DC test unit 3 comprises a decision device 3A for comparing a voltage or a current taken out from the memory with a reference value and a failure analysis memory 3B for storing therein a failure address of the memory.


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