The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2000

Filed:

Jul. 16, 1998
Applicant:
Inventors:

H C Tseng, Hsinchu, TW;

Kun-Cho Chen, Taichung Hsien, TW;

Heng-Sheng Huang, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257408 ; 257408 ; 257412 ; 257433 ; 257344 ; 257336 ; 257900 ;
Abstract

A MOSFET device protects the device from the short channel effect and decrease the resistance of a gate of the device. The MOSFET device includes a gate formed on a substrate and two source/drain regions. The source/drain regions are formed in the substrate at the sides of the gate. An oxide layer includes a first structure and a second structure. The first structure is at the side walls of the gate with the top of the first structure being lower than the top of the gate. The second structure is formed on the substrate and is connected to the first structure. A first spacer is formed on the second structure and beside the first structure. A second spacer is formed on the second structure and beside the first spacer. A self-aligned metal layer is formed on the gate, the first spacer, and over the substrate. As a result, the MOSFET device has an ultra-shallow junction under the first spacer to reduce the source/drain resistance and increase the operating rate of the device.


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