The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2000

Filed:

Jan. 12, 1999
Applicant:
Inventors:

Lei Zhang, San Jose, CA (US);

William Chou, Cupertino, CA (US);

Michael G Peters, Santa Clara, CA (US);

Solomon I Beilin, San Carlos, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K / ;
U.S. Cl.
CPC ...
216 17 ; 216 13 ; 216 18 ; 216 39 ;
Abstract

Processes for forming conductive vias between circuit elements formed on either side of a flexible substrate are disclosed. In one embodiment, the inventive process starts with a flexible film polyimide substrate on each side of which is arranged a layer of copper. Both of the copper surfaces are coated with photoresist. Blind vias are then drilled through the top copper layer and substrate using a laser. The photoresist is then exposed (patterned). A plating operation is used to fill the vias with a conductive material. The resist is then developed and the line and pad structures on the surface of the copper layer are plated. The photoresist is then stripped. In a variation of this embodiment, the photoresist is imaged prior to drilling of the vias using a laser. In an alternative embodiment of the inventive process, a through hole is drilled instead of a blind via. In either embodiment, there is no process step between the photo-exposure of the resist and the laser drilling which can impact the dimensions of the substrate.


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