Efficient semiconductor burn-in circuit and method of operation

Abstract

The disclosed invention provides a circuit and burn-in test method for semiconductor devices that increases the speed of burn-in tests. The present invention accomplishes this by causing each of the devices under test to be tested multiple times (from 2 to 32+ times) during each power cycle. By such multiple cycling of the unit under test, during the power cycle, the total test time is shortened. It has also been found that the devices tested in accordance with the present invention are more efficiently stressed and have a reliability greater than devices passing the prior art tests. In accordance with the invention, the memory or logic devices under test are provided with a respective clock means that will operate each of the devices under test through multiple (from 2 to 32+ times) write and read operations during each power cycle. Data coherency for each read operation is provided as is the inversion of data if any fail is recorded during a read operation. Accordingly, the present invention provides a burn-in test that more efficiently stresses semiconductor devices such as memory or logic units, by a factor of up to 32. The invention utilizes the internal clock of a semiconductor device by cycling that clock x times during the period of each external clock cycle in the burn-in test and simultaneously synchronizes these internal cycles with the test cycle, thereby providing coherent data for each internal cycle.