The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2000

Filed:

Feb. 23, 1996
Applicant:
Inventors:

Alexander D Peleg, Haifa, IL;

Millind Mittal, South San Francisco, CA (US);

Larry M Mennemeier, Boulder Creek, CA (US);

Benny Eitan, Haifa, IL;

Carole Dulong, Saratoga, CA (US);

Eiichi Kowashi, Ryugasaki, JP;

Wolf Witt, Walnut Creek, CA (US);

Derrick Chu Lin, Foster City, CA (US);

Ahmet Bindal, Sunnyvale, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ; G06F / ;
U.S. Cl.
CPC ...
708523 ; 708603 ; 708626 ; 395562 ; 39580042 ;
Abstract

A processor having a first and second storage having a first and second packed data, respectively. Each packed data includes a first, second, third, and fourth data element. A multiply-add circuit is coupled to the first and second storage areas. The multiply-add circuit includes a first, second, third, and fourth multiplier, wherein each of the multipliers receives a corresponding set of said data elements. The multiply-add circuit further includes a first adder coupled to the first and second multipliers, and second adder coupled to the third and fourth multipliers. A third storage area is coupled to the adders. The third storage area includes a first and second field for saving output of the first and second adders, respectively, as first and second data elements of a third packed data.


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