Enhancing dmos device ruggedness by reducing transistor parasitic

Abstract

This invention discloses a vertical DMOS power device formed in a semiconductor substrate with a top surface and a bottom surface. The power device includes a core cell area and a gate runner area. The power device includes a plurality of vertical DMOS transistor cells disposed in the core cell area wherein each transistor cell includes a drain of a first conductivity type disposed at the bottom surface of the substrate. Each of the DMOS transistor cells further includes a trench surrounding the cell having a polysilicon disposed in the trench defining a gate for the transistor cell. Each of the transistor cells further includes a source region of the first conductivity type disposed in the substrate near the gate. Each of the transistor cells further includes a body region of a second conductivity type disposed in the substrate between the gate wherein the body region defining a vertical current channel along the trench between the source and the drain. The power device further includes a plurality of trenched polysilicon fingers extended from the trenched gate to the gate runner area. The power device further includes a plurality of ruggedness enhancing body dopant regions of the second conductivity type disposed in the substrate between the trenched polysilicon fingers and in a termination, each of the ruggedness enhancing body dopant regions further includes a breakdown-inducing-regions disposed at bottom of the body dopant region at a depth below the trenched gate-extension fingers having a higher dopant concentration of the second conductivity type for inducing a breakdown therein. In a preferred embodiment, each of the vertical DMOS further includes a deep high concentration dopant region disposed in the body region below the source having a higher dopant concentration than the body region.