Nitride spacer technology for flash eprom

Abstract

A flash EPROM device includes a floating gate electrode with a top surface and sidewalls is formed on a gate oxide layer covering a semiconductor substrate. A polyoxide cap layer is formed on the top surface of the floating gate electrode. A blanket tunnel oxide layer covers the cap layer, the sidewalls of the floating gate electrode, and the exposed surfaces of the gate oxide layer. A spacer structure is formed on the surface of the tunnel oxide layer adjacent to the sidewalls of the floating gate electrode and above the gate oxide layer. A dielectric, silicon nitride inner spacer, having an annular or an L-shaped cross section, is formed on the blanket tunnel oxide layer adjacent to the sidewalls of the floating gate electrode. In the case of the L-shaped cross section inner spacer, an outer dielectric, spacer is formed over the inner dielectric, spacer. A blanket interelectrode dielectric layer covers the blanket tunnel oxide layer, and the spacer structure. A control gate electrode is formed over the interelectrode dielectric layer on one side of the floating gate electrode.