The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 15, 2000
Filed:
May. 06, 1997
See-Hack Foo, Fremont, CA (US);
Rhea Posedel, Belmont, CA (US);
Larry Lape, Mountain View, CA (US);
James Wrenn, Palo Alto, CA (US);
Ernie Wang, San Mateo, CA (US);
Paul Burke, Hayward, CA (US);
Carl Buck, Cupertino, CA (US);
AEHR Test Systems, Mountain View, CA (US);
Abstract
A reusable carrier 10 for temporarily holding an integrated circuit 12 during burn-in and electrical test includes a base 14 and a lid 16 attached to the base 14 by hinges 18. A flexible substrate 19 is attached to the base 14. Alignment posts 20 have tapered surfaces 22 that engage corners 24 of the integrated circuit 12 to position the integrated circuit 12 precisely on upper surface 26 of the substrate 19. A spring-loaded latch 28 engages projection 30 in aperture 32 of the base 14 to hold the lid 16 closed over the integrated circuit 12. Electrically conductive traces 34 on the surface 26 have contact bumps which engage contact pads on the underside of the integrated circuit 12 to connect the integrated circuit 12 to peripheral contact pads 38 around edges 40 of the substrate 19. A spring 42 engages upper surface 43 of the integrated circuit 12 when the lid 16 is in its closed position over the integrated circuit 12, to provide a biasing force to urge the contact pads against the conductive traces 34 with sufficient force to insure a reliable electrical connection. For burn-in, the temporary package 10 containing the integrated circuit die 12 is now loaded into a socket 48 on a burn-in board 50, which is then loaded into a burn-in system, where otherwise standard burn-in is performed.