The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 15, 2000

Filed:

Oct. 30, 1997
Applicant:
Inventors:

Kazuto Tsuji, Kawasaki, JP;

Yoshiyuki Yoneda, Kawasaki, JP;

Hideharu Sakoda, Kawasaki, JP;

Ryuuji Nomoto, Kawasaki, JP;

Eiji Watanabe, Kawasaki, JP;

Seiichi Orimo, Kawasaki, JP;

Masanori Onodera, Kawasaki, JP;

Junichi Kasai, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
257786 ; 257787 ; 257790 ; 257778 ; 257691 ; 257697 ; 257698 ; 257668 ; 257676 ;
Abstract

This invention relates to a semiconductor device in which a plurality of outer terminals are arranged in a lattice formation on a flat surface. The semiconductor device comprises a semiconductor chip having a plurality of pads, a resin portion sealing said semiconductor chip and a terminal portion in which a prescribed number of pole terminals electrically connected to said pads provided in said semiconductor chip are provided, said pole terminals being exposed from said resin portion. According to the invention, a cost for production is reduced and a reliability and electrical characteristics can be improved.


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