The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 15, 2000
Filed:
Nov. 06, 1997
Fwu-Iuan Hshieh, Saratoga, CA (US);
Koon Chong So, San Jose, CA (US);
Mageposer Semiconductor Corporation, San Jose, CA (US);
Abstract
This invention discloses a MOSFET power device supported on a substrate. The MOSFET power device includes a plurality polysilicon-with-oxide-cap segments disposed over a gate oxide layer including two outermost segments and a plurality of inner segments include a plurality of gate oxide-plug openings. Each of the inner segments functions as agate and the two outer most segments function as a field plate and an equal potential ring separated by a termination oxide-plug gap and the gate oxide-plug openings and the termination oxide-plug gap having an aspect ratio greater or equal to 0.5. The MOSFET power device further includes a plurality of MOSFET transistor cells for each of the gates, wherein each transistor cells further includes a source region, a body region, the transistor cells further having a common drain disposed at a bottom surface of the substrate. Each of the inner segments functions as a gate having a side wall spacer surrounding edges of the inner segments, and the gate oxide-plug openings and the termination oxide-plug gap being filled with an oxide plug. The MOSFET transistor cells are covered by an overlying insulation layer having a plurality of contact openings defined therein. The MOSFET power device further includes a plurality of metal segments covering the overlying insulation layer and being in electric contact with the DMOS device through the contact opening. The MOSFET power device further includes a plurality of deep-and-narrow gaps between the metal segments wherein each gap having an aspect ratio equal to or greater than 0.5.